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order this document by m68000umad/ad this document contains information on a product under development. motorola reserves the right to change or discontinue this pr oduct without notice. addendum to m68000 user manual m68000 1997 motorola, inc. all rights reserved. communications and advanced consumer technologies group semiconductor product information august 7, 1997 this addendum to the m68000um/ad users manual , revision 8, provides corrections to the original text as well as additional information. this document and other information on this product is maintained on the world wide web at http://www.motorola.com/68000. overview this manual includes hardware details and programming information for the mc68hc000, the mc68hc001, the mc68ec000, and the mc68sec000. for ease of reading, the name m68000 mpus will be used when referring to all processors. refer to m68000pm/ad, m68000 programmer's reference manual , for detailed information on the mc68000 instruction set. the four microprocessors are very similar to each other and all contain the following features: ? sixteen 32-bit data and address registers ? 16-mbyte direct addressing range ? program counter ? 6 instruction types ? operations on five main data types ? memory-mapped input/output (i/o) ? 14 addressing modes the following processors contain additional features: ? mc68hc001/mc68ec000/mc68sec000 statically selectable 8- or 16-bit data bus ? mc68hc000/mc68ec000/mc68hc001/mc68sec000 low power
2 m68000 users manual addendum motorola the primary features of the mc68sec000 embedded processor include the following: ? direct replacement for the mc68ec000 pin-for-pin compatibility with the mc68ec000 in the plastic qfp and tqfp packages vast selection of existing third-party development tools for the mc68ec000 support the mc68sec000 software written for the mc68ec000 will run unchanged on the mc68sec000 ? power management low-power hcmos technology static design allows for stopping the processor clock 3.3v or 5v operation typical 0.5 m a current consumption at 3.3v in sleep mode ? software strength fully upward object-code compatible with other m68000 family products m68000 architecture allows effective assembly code with a c compiler ? upgrade fully upward code-compatible with higher performance 680x0 and 68300 family members coldfire ? code-compatible with minor modifications 1. mc68hc000 the primary benefit of the mc68hc000 is reduced power consumption. the device dissipates less power (by an order of magnitude) than the nmos mc68000. the mc68hc000 is an implementation of the m68000 16/-32 bit microprocessor architecture. the mc68hc000 has a 16-bit data bus implementation of the mc68000 and is upward code-compatible with the mc68010 and the mc68020 32-bit implementation of the architecture. 1.1 mc68hc001 the mc68hc001 provides a functional extension to the mc68hc000 hcmos 16-/32-bit microprocessor with the addition of statically selectable 8- or 16-bit data bus operation. the mc68hc001 is object-code compatible with the mc68hc000. you can migrate code written for the mc68hc001 without modification to any member of the m68000 family. 1.2 mc68ec000 the mc68ec000 is an economical high-performance embedded controller designed to suit the needs of the cost-sensitive embedded-controller market. the hcmos mc68ec000 has an internal 32-bit architecture that is supported by a statically selectable 8- or 16-bit data bus. this architecture provides a fast and efficient processing device that can satisfy the requirements of sophisticated applications based on high-level languages. the mc68ec000 is fully object-code compatible with the mc68000. you can migrate code written for the mc68ec000 without modification to any member of the m68000 family. the mc68ec000 brings the performance level of the m68000 family to cost levels previously associated with 8-bit microprocessors. the mc68ec000 benefits from the rich m68000 instruction set and its related high code density with low memory bandwidth requirements.
motorola m68000 users manual addendum 3 1.3 mc68sec000 the mc68sec000 is a cost-effective static embedded processor engineered for low-power applications. in addition to providing the substantial cost and performance benefits of the mc68ec000, the low-power mode of the mc68sec000 provides significant advantages in power consumption and power management. the typical current consumption of the mc68sec000 is only 0.5 m a in static standby mode and 15.0ma in normal 3.3v operation. the mc68sec000 operates in either 3.3v or 5.0v systems. the remarkably low power consumption, small footprint packages, and static implementation are combined in the mc68sec000 for low- power applications such as portable measuring equipment, electronic games, and battery-operated hand-held consumer products. the hcmos mc68sec000s static architecture is a direct replacement for the mc68ec000, which offers the lowest cost entry point to 32-bit processing. the internal 32-bit architecture provides fast and efficient processing that satisfies the requirements of sophisticated applications based on high-level languages. all of the existing third-party developer tools widely available for the mc68ec000 will directly support the mc68sec000. you can find detailed descriptions of these tools in the high performance embedded systems source catalog .
4 m68000 users manual addendum motorola 2.0 signal description change figure 3-3 on page 3-2. figure 1. input and output signals (mc68ec000 and mc68sec000) 2.1 data bus (d15-d0) in section 3.2 on page 3-4, replace the mc68ec000 and mc68hc001 use d7-d0 in 8-bit mode, and d15- d8 are undefined. with using the mc68hc001, mc68ec000, and mc68sec000 mode pin, you can statically select either 8- or 16-bit modes for data transfer. the mc68ec000, mc68sec000, and mc68hc001 use d7-d0 in 8-bit mode. d15-d8 are undefined. 2.2 bus arbitration control in section 3.4 on page 3-5, the sentence in the 48-pin version of the mc68008 and mc68ec000, no pin is available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration scheme. should read in the 64-pin mc68ec000 and mc68sec000, no pin is available for the bus grant acknowledge signal. these microprocessors use a two-wire bus arbitration scheme. 2.3 system control the mode subsection heading of section 3.6 on page 3-7 should read mode (mode) (mc68hc001/ 68ec000/68sec000). 2.4 mc68sec000 low-power mode add the following to sections 4 and 5, bus operation. the mc68sec000 has been redesigned to provide fully static- and low-power operation. this section describes the recommended method for placing the mc68sec000 into a low-power mode to reduce the address bus data bus asynchronous bus control bus arbitration control interrupt control processor status a23-a0 d15-d0 as r/w uds lds dtack berr reset halt mode system control v cc gnd clk mc68sec000 fc0 fc1 fc2 ipl0 ipl1 ipl2 avec br bg
5 m68000 users manual addendum motorola power consumption to its quiescent value 1 while maintaining the internal state of the processor. the low-power mode described below will be routinely tested as part of the mc68sec000 test vectors provided by motorola. to successfully enter the low-power mode, the mc68sec000 must first be in the supervisor mode. a recommended method for entering the low-power mode is to use the trap instruction, which causes the processor to begin exception processing, thus entering the supervisor mode. external circuitry should accomplish the following steps during the trap routine: 1. externally detect a write to the low-power address. you select this address which can be any address in the 16 mbyte addressing range of the mc68sec000. a write to the low-power address can be detected by polling a23Ca0, r/w , and fc2Cfc0. when the low-power address is detected, r/w is a logic low, and the function codes have a five (101) on their output, the processor is writing to the low-power address in supervisor mode and user-designed circuitry should assert the address_match signal shown in figure 2 and figure 3. figure 3. mc68sec000 low-power circuitry for 8-bit data bus 2. execute the stop instruction. the external circuitry shown in figure 2 and figure 3 will count the number of bus cycles starting with the write to the low-power address and will stop the processor clock on the first falling edge of the system clock after the bus cycle that reads the immediate data of the stop instruction. figure 3 has one more flip-flop than figure 2 because the mc68sec000 in 1. the preliminary speci?cation for the mc68sec000s current drain while in the low-power mode is idd < 2 m a for 3.3v operation and idd < 5 m a for 5.0v operation. figure 2. mc68sec000 low-power circuitry for 16-bit data bus d q q cl ck d q ck d q ck address_match as restart reset cpu_clk system_clk q q as cl d q q cl ck d q q cl ck d q q ck address_match restart reset cpu_cl k d q q cl ck system_clk as as as
6 m68000 users manual addendum motorola 8-bit mode requires two bus cycles to fetch the immediate data of the stop instruction. after the processor clock is disabled, it is often necessary to disable the clock to other sections of your circuit. this can be done, but be careful that runt clocks and spurious glitches are not presented to the mc68sec000. a timing diagram is shown in figure 4. figure 4. mc68sec000 clock stop timing for 16-bit data bus note: while the mc68sec000 is in the low-power mode, all inputs must be driven to v dd or v ss , or have a pull-up or pull-down resistor. 3. this step is optional depending on whether your applications require the mc68sec000 signals with three-state capability to be placed into a high-impedance state. to place the mc68sec000 into a three-state condition, the proper method for arbitrating the bus (as described in 5.2 bus arbitration in the m68000 users manual, rev 8 ) s hould be completed during the fetch of the status register data for the stop instruction. a timing diagram with the bus arbitration sequence is shown in figure 5. figure 5. mc68sec000 clock stop timing with bus arbitration for 16-bit data bus write to low-power address fetch immediate data of stop instruction stop clk s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 cpu_clk dtack rw as br bg clk s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 cpu_clk dtack rw as write to low-power a dd r ess fetch immediate data of stop instruction stop
7 m68000 users manual addendum motorola after the previous steps are completed, the mc68sec000 will remain in the low-power mode until it recognizes the appropriate interrupt . external logic will also have to poll iplb2Ciplb0 to detect the proper interrupt. when the correct interrupt level is received, the following steps will bring the processor out of the low-power mode: 1. restart the system clock if it was stopped. 2. wait for the system clock to become stable. 3. assert the restart signal. this will cause the processors clock to start on the next falling edge of the system clock. figure 6 shows the timing for bringing the processor out of the low-power mode. both the restart and reset signals are subject to the asynchronous setup time as specified in the electrical characteristics section of this addendum. warning the system clock must be stable before the restart signal is asserted to prevent glitches in the clock. an unstable clock can cause unpredictable results in the mc68sec000. figure 6. mc68sec000 clock start timing 4. if the mc68sec000 was placed in a three-state condition, the br signal must be negated before the processor can begin executing instructions. clk cpu_clk restart
8 m68000 users manual addendum motorola an example trap routine is as follows: trap_x move.b #0,$low_power_address /* write that causes address_match to assert */ stop #$2000 /* stop instruction with desired interrupt mask */ rte /* return from the exception */ the first instruction (move.b #0,$low_power_address) writes a byte to the low-power address that will cause the external circuitry to begin the sequence that will stop the processors clock. the second instruction (stop #$2000) loads the sr with the immediate data. this lets you set the interrupt that will cause the processor to come out of the low-power mode. the final instruction (rte) tells the processor to return from the exception and resume normal processing. 3.0 mc68sec000 electrical specifications add to the following table to section 10.1. 3.1 mc68sec000 maximum ratings 3.2 cmos considerations the following change should be made to section 10.4, cmos considerations. although the mc68hc000 and mc68ec000 is implemented with input protection diodes, care should be exercised to ensure that the maximum input voltage specification is not exceeded. should read although the mc68hc000, mc68ec000, and mc68sec000 are implemented with input protection diodes, be careful not to exceed the maximum input voltage specification. rating symbol value unit supply voltage v cc C0.3 to 6.5 v input voltage v in C0.5 to 6.5 v maximum operating temperature range commercial extended "c" grade t a t l to t h 0 to 70 C40 to 85 c storage temperature tstg C55 to 150 c
9 m68000 users manual addendum motorola 4.0 mc68sec000 ac electrical specifications replace figure 10-2 on page 10-6 with figure 7. figure 7. drive levels and test points for ac speci?cations - applies to all parts 0.8 v 2.0 v b drive to 0.5 v 2.0 v 0.8 v valid output n valid output n + 1 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v valid output n valid output n+1 2.0 v 0.8 v b a valid input 2.0 v 0.8 v 2.0 v 0.8 v d c drive to 0.5 v drive to 2.4 v valid input 2.0 v 0.8 v 2.0 v 0.8 v d c drive to 0.5 v drive to 2.4 v 2.0 v 0.8 v 2.0 v 0.8 v f clk outputs(1) clk outputs(2) clk inputs(3) clk inputs(4) clk all signals(5) notes: 1. this output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. this output timing is applicable to all parameters specified relative to the falling edge of the clock. 3. this input timing is applicable to all parameters specified relative to the rising edge of the clock. 4. this input timing is applicable to all parameters specified relative to the falling edge of the clock. 5. this timing is applicable to all parameters specified relative to the assertion/negation of another signal. legend: a. maximum output delay specification. b. minimum output hold time. c. minimum input setup time specification. d. minimum input hold time specification. e. signal valid to signal valid specification (maximum or minimum). f. signal valid to signal invalid specification (maximum or minimum). drive to 2.4 v e a
10 m68000 users manual addendum motorola 5.0 mc68sec000 dc electrical specifications add the following table to section 10.13 on page 10-23. (v cc = 5.0 vdc 5%, 3.3 vdc 10%,; gnd = 0 vdc; t a = t l to t h ) *during normal operation, instantaneous vcc current requirements may be as high as 1.5a. currents listed are with no loading. **capacitance is periodically sampled rather than 100% tested. 3.3 v 5.0 v characteristic symbol min max min max unit input high voltage v ih 2.0 v cc 2.0 v cc v input low voltage v il gnd 0.8 gnd C 0.5 0.8 v input leakage current berr , br , dtack , clk, i pl2 -ipl0 , avec mode, halt , reset iin 2.5 20 2.5 20 ua three-state (off state) input current i tsi 2.5 2.5 ua output high voltage v oh 2.4 v cc C0.75 v output low voltage (iol = 1.6 ma) halt (iol = 3.2 ma) a23Ca0, bg , fc2Cfc0 (iol = 5.0 ma) reset (iol = 5.3 ma) as , d15Cd0, lds , r/w , uds v ol 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 v current dissipation* f = 0 hz i d 0.7 1.0 ma f=10mhz 10 15 ma f=16 mhz 15 25 ma f= 20 mhz 20 30 ma capacitance (vin = 0 v, t a = 25 c, frequency = 1 mhz)** cin 20.0 20.0 pf load capacitance halt all others cl 70 130 70 130 pf
11 m68000 users manual addendum motorola 6.0 mc68sec000 ac electrical specifications clock timing (see figure 2) add the following table and figure 8 to section 10.9 on page 10-9. applies to 3.3v and 5v. figure 8. mc68sec000 clock input timing diagram 10mhz 16mhz 20mhz num. characteristic symbol min max min max min max unit frequency of operation f 0 10.0 0 16.7 0 20.0 mhz 1 cycle time tcyc 100 60 50 ns 2,3 clock pulse width t cl t ch 45 45 27 27 21 21 ns 4,5 clock rise and fall times t cr t cf 10 10 5 5 4 4 ns 0.8 v 2.0 v 4 5 1 2 3 note: timing measurements are referenced to and from a low voltage of 0.8 v and a high voltage of 2.0 v, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 v and 2.0 v.
12 m68000 users manual addendum motorola 7.0 mc68sec000 ac electrical specifications read and write cycles add the following table and figures 9 and 10 to section 10.16. applies to 3.3v and 5v. (gnd = 0 v; t a = t l to t h ; see figures 3 and 4) num characteristic 10mhz 16mhz 20mhz unit min max min max min max 6 clock low to address valid 35 30 25 ns 6a clock high to fc valid 0 35 0 30 0 25 ns 7 clock high to address, data bus high impedance (maximum) (write) 555042ns 8 clock high to address, fc invalid (minimum) 000ns 9 1 clock high to as , lds , uds asserted 3 35 3 30 3 25 ns 11 2 address valid to as , lds , uds asserted (read)/ as asserted (write) 201510ns 11a 2 fc valid to as , lds , uds asserted (read)/ as asserted (write) 45 45 40 ns 12 1 clock low to as , lds , uds negated 3 35 3 30 3 25 ns 13 2 as , lds , uds negated to address, fc invalid 15 15 10 ns 14 2 as (and lds , uds read) width asserted 195 120 100 ns 14a 2 lds , uds width asserted (write) 95 60 50 ns 15 2 as , lds , uds width negated 105 60 50 ns 16 clock high to control bus high impedance 55 50 42 ns 17 2 as , lds , uds negated to r/w invalid 15 15 10 ns 18 1 clock high to r/w high (read) 0 35 0 30 0 25 ns 20 1 clock high to r/w low (write) 0 35 0 30 0 25 ns 20a 2,6 as asserted to r/w low (write) 10 10 10 ns 21 2 address valid to r/w low (write) 000ns 21a 2 fc valid to r/w low (write) 50 30 25 ns 22 2 r/w low to ds asserted (write) 50 30 25 ns 23 clock low to data-out valid (write) 35 30 25 ns 25 2 as , lds , uds negated to data-out invalid (write) 30 15 10 ns 26 2 data-out valid to lds , uds asserted (write) 30 15 10 ns 27 5 data-in valid to clock low (setup time on read) 555ns 28 2 as , lds , uds negated to dtack negated (asynchronous hold) 0 110 0 110 0 95 ns 28a clock high to dtack negated 0 110 0 110 0 95 ns
13 m68000 users manual addendum motorola ac electrical specifications read and write cycles (continued) applies to 3.3v and 5v. notes: 1. for a loading capacitance of less than or equal to 50 pf, subtract 5 ns from the value given in the maximum columns. 2. actual value depends on clock period. 3. if #47 is satis?ed for both dt a ck and berr , #48 may be ignored. in the absence of dt a ck , berr is an asynchronous input using the asynchronous input setup time (#47). 4. for power-up, the mc68sec000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. after th e system is powered up, #56 refers to the minimum pulse width required to reset the controller. 5. if the asynchronous input setup time (#47) requirement is satis?ed for dt a ck , the dt a ck asserted to data setup time (#31) requirement can be ignored. the data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. 6. when as and r/w are equally loaded ( 20%), subtract 5 ns from the values given in these columns. 7. the minimum value must be met to guarantee proper operation. if the maximum value is exceeded, bg may be reasserted. num characteristic 10mhz 16mhz 20mhz unit min max min max min max 29 as , lds , uds negated to data-in invalid (hold time on read) 000ns 29a as , lds , uds negated to data-in high impedance (read) 150 90 75 ns 30 as , lds , uds negated to berr negated 000ns 31 2,5 dtack asserted to data-in valid (setup time on read) 65 50 42 ns 32 halt and reset input transition time 0 150 0 150 0 150 ns 33 clock high to bg asserted 35 30 25 ns 34 clock high to bg negated 35 30 25 ns 35 br asserted to bg asserted 1.5 3.5 1.5 3.5 1.5 3.5 clks 36 7 br negated to bg negated 1.5 3.5 1.5 3.5 1.5 3.5 clks 38 bg asserted to control, address, data bus high impedance (as negated) 555042ns 39 bg width negated 1.5 1.5 1.5 clks 44 as , lds , uds negated to avec negated 0 55 0 50 0 42 ns 47 5 asynchronous input setup time 555ns 48 2,3 berr asserted to dtack asserted 20 10 10 ns 52 data-in hold from clock high 000ns 53 data-out hold from clock high (write) 000ns 55 r/w asserted to data bus impedance change (write) 20 10 0 ns 56 4 halt , reset pulse width 10 10 10 clks 58 7 br negated to as , lds , uds , r/w driven 1.5 1.5 1.5 clks 58a 7 br negated to fc driven 111 clks
14 m68000 users manual addendum motorola figure 9. mc68sec000 read cycle timing diagram 6a 8 6 13 14 12 17 18 47 28 29 27 48 47 30 47 32 56 47 32 s0 s1 s2 s3 s4 s5 s6 clk fc2?c0 a23?0 as lds / uds r/w dtack data in berr / br (note 2) halt / reset 47 asynchronous inputs (note 1) s7 31 7 11 11a notes: 1. setup time for the asynchronous inputs ipl2?pl0 and avec (#47) guarantees their recognition at the next falling edge of the clock. 2. br need fall at this time only to insure being recognized at the end of the bus cycle. 3. timing measurements are referenced to and from a low voltage of 0.8 v and a high voltage of 2.0 v, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 v and 2.0 v. 9 15
motorola m68000 users manual addendum 15 figure 10. mc68sec000 write cycle timing diagram 6a 8 6 15 13 9 14 12 17 18 47 28 25 26 48 47 30 47 32 56 47 32 s0 s1 s2 s3 s4 s5 s6 clk fc2?c0 a23?0 as lds / uds r/w dtack data out berr / br (note 2) halt / reset 47 asynchronous inputs (note 1) s7 23 7 11 9 53 7 55 21 22 20 11a 21a notes: 1. timing measurements are referenced to and from a low voltage of 0.8 v and a high voltage of 2.0 v, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 v and 2.0 v. 2. because of loading variations, r/w may be valid after as even though both are initiated by the rising edge of s2 (specification #20a). 14a 20a
16 m68000 users manual addendum motorola 8.0 mc68sec000 ac electrical specifications bus arbitration add the following table and figure 11 to section 10.17. (gnd = 0 vdc; t a = t l to t h ; refer to figure 13) applies to 3.3v and 5v. 1. the minimum value must be met to guarantee proper operation. if the maximum value is exceeded, bg may be reasserted. num characteristicp 10mhz 16mhz 20mhz unit min max min max min max 7 clock high to address, data bus high impedance (maximum) 55 50 42 ns 16 clock high to control bus high impedance 55 50 42 ns 33 clock high to bg asserted 0 35 0 30 0 25 ns 34 clock high to bg negated 0 35 0 30 0 25 ns 35 br asserted to bg asserted 1.5 3.5 1.5 3.5 1.5 3.5 clks 36 br negated to bg negated 1.5 3.5 1.5 3.5 1.5 3.5 clks 38 bg asserted to control, address, data bus high impedance (as negated) 555042ns 39 bg width negated 1.5 1.5 1.5 clks 47 asynchronous input setup time 555ns 58 1 br negated to as , lds , uds , r/w driven 1.5 1.5 1.5 clks 58a 1 br negated to fc driven 111 clks
motorola m68000 users manual addendum 17 figure 11. bus arbitration timing figure 12. mc68sec000 bus arbitration timing diagram 36 39 34 38 33 35 clk note: setup time to the clock (#47) for the asynchronous inputs berr, br, dtack, ipl2-ipl0, and vpa guarantees their recognition at the next falling edge of the clock. br bg and r/w strobes clk 33 35 br bg as ds r/w fc2?c0 a19?0 d7?0 47 38 36 58 note: waveform measurements for all inputs and outputs are specified at: logic high 2.0 v, logic low = 0.8 v. 34 58a 39 a23 d15 lds /uds
18 m68000 users manual addendum motorola figure 13. bus arbitration timingidle bus case clk 47 35 34 38 br bg as ds vma r/w fc2-fc0 a23-a0 d15-d0 notes: waveform measurements for all inputs and outputs are specified at: logic high 2.0 v, logic low = 0.8 v. this diagram al so applies to the 68ec000. 33
motorola m68000 users manual addendum 19 figure 14. bus arbitration timing - active bus case clk 47 33 35 34 16 br bg as ds vma r/w fc2-fc0 a23-a0 d15-d0 note: waveform measurements for all inputs and outputs are specified at: logic high 2.0 v, logic low = 0.8 v. this diagram also applies to the 68ec000. 7
20 m68000 users manual addendum motorola figure 15. bus arbitration - multiple bus request clk 33 35 57a br bg as ds vma r/w fc2-fc0 a23-a0 d15-d0 47 39 39 38 36 58 notes: waveform measurements for all inputs and outputs are specified at: logic high 2.0 v, logic low = 0.8 v. this diagram also applies to the 68ec000.
motorola m68000 users manual addendum 21 9.0 mechanical data 9.1 pin assignments add figure 12 to section 11.1. the following defines the pin assignment and the package dimensions of the 64 lead qfp (fu package) and 64 lead tqfp (pb package) for the mc68sec000. note that it is pin-to-pin compatible with the mc68ec000. figure 16. 64-lead quad flat pack and 64-lead thin quad flat pack r/w 64 17 32 33 16 148 49 dtack bg br v cc v cc clk gnd mode halt reset avec berr ipl2 ipl1 ipl0 fc2 d12 d13 d14 d15 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 d4 lds uds as d0 d1 d2 d3 gnd d5 d6 d7 d8 d9 d10 d11 a4 fc1 fc0 a0 a1 a2 a3 gnd a5 a6 a7 a8 a9 a10 a11 a12 mc68sec000fu/pb
22 m68000 users manual addendum motorola 10.0 package dimensions - fu suffix this diagram replaces the one on page 11-16 64 lead quad flat pack case 840b-01 dim millimeters inches min max min max a 16.95 17.45 0.667 0.687 b 13.90 14.10 0.547 0.555 c 16.95 17.45 0.667 0.687 d 13.90 14.10 0.547 0.555 g 0.30 0.45 0.012 0.018 h 0.80 bsc 0.031 bsc k 2.15 2.45 0.085 0.096 l 0.13 0.23 0.005 0.009 m 2.00 2.40 0.79 0.094 r 12.00 ref 0.472 ref s 12.00 ref 0.472 ref g r d c h m k l b s a
motorola m68000 users manual addendum 23 11.0 package dimensions - pb suffix add the following to section 11.2. 64 lead thin quad flat pack case 840f-02 dim millimeters inches min max min max a 12.00 bsc 0.472 bsc a1 6.00 bsc 0.236 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c 12.00 bsc 0.472 bsc c1 6.00 bsc 0.236 bsc d 10.00 bsc 0.394 bsc d1 5.00 bsc 0.197 bsc g 0.17 0.27 0.007 0.011 h 0.50 bsc 0.020 bsc k --- 1.60 --- 0.063 l 0.09 0.20 0.004 0.008 m 1.35 1.45 0.053 0.057 g d d1 c1 c h m k l b b1 a1 a
24 m68000 users manual addendum motorola 12.0 package/frequency availability replaces section 11.1 the following tables identify the packages and operating frequencies available for the mc68hc000, mc68hc001, mc68ec000, and the mc68sec000. note : ** not recommended for new designs mc68sec000 package frequency voltage 3.3 v 5 v quad flat pack (fu) thin quad flat pack (pb) 10 mhz 16 mhz 20mhz 3 3 3 3 3 3 10 mhz 16 mhz 20mhz 3 3 3 3 3 3 mc68hc000 package frequency voltage 5v plastic dip plastic quad pack (plcc) plastic quad (gull wing)** pin grid array, solder lead finish** pin grid array, gold lead finish** 8,10,12,16,20 mhz 3 8,10,12,16,20 mhz 3 8,10,12,16,20 mhz 3 8,10,12,16,20 mhz 3 plastic quad pack (plcc) 8,10,12,16,20 mhz 3 mc68hc001** package frequency voltage 5v plastic quad pack (plcc) plastic quad (gull wing) pin grid array, gold lead finish 8,10,12,16 mhz 3 8,10,12,16 mhz 3 8,10,12,16 mhz 3 8,10,12,16 mhz 3 mc68ec000 package frequency voltage 5v plastic quad pack (plcc) plastic quad flat pack 8 mhz 3 10 mhz 3 12 mhz 3 16 mhz 3 20 mhz 3
motorola m68000 users manual addendum 25 ordering information add the following to section 11. the following tables contains the ordering information for the mc68sec000. documentation add to section 11. the documents listed in the following table contain detailed information that pertain to the mc68sec000 processor. you can obtain these documents from the literature distribution centers listed on the last page of this document. mc68sec000 ordering information package body size lead spacing speed (in mh z) voltage suffix temperature range qfp 14.0 mm x 14.0mm 0.8mm 10/16/20 mhz 3.3v or 5.0v fu 0c to +70c cfu -40c to +85c tqfp 10.0mm x 10.0mm 0.5mm pb 0c to +70c cpb -40c to +85c mc68hc000 ordering information package body size lead spacing speed (in mhz) voltage suffix temperature range dip 81.91mm x 20.57mm 2.54mm 8, 10, 12, 16 5.0v p 0c to +70c plcc 25.57mm x 25.27mm 1.27mm 8, 10, 12, 16, 20 fn 0c to +70c 8, 10, 12, 16 cfn -40c to +85c mc68ec000 ordering information package body size lead spacing speed (in mhz) voltage suffix temperature range plcc 25.57mm x 25.27mm 1.27mm 8, 10,12, 16, 20 5.0v fn 0c to +70c pqfp 14.1mm x 14.1mm 0.8mm 8, 10,12, 16, 20 fu mc68sec000 documentation mc68sec000 documentation document number m68000 family programmers reference manual m68000pm/ad m68000 users manual m68000um/ad high performance embedded systems source catalog br729/d mc68ec000 product brief mc68ec000/d mc68sec000 product brief mc68sec000/d
semiconductor product information motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" para meters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's tec hnical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authoriz ed for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any othe r application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufac ture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. literature distribution centers: usa/europe: motorola literature distribution; p.o. box 20912, arizona 85036. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbour center, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong.

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